Awaiting product image

Lab Workshop ‘FPGA Architecture and Programming using Verilog HDL’ – Batch 6

 

 

SKU: NIELIT WORKSHOP | Starts on 28th December 2022 Category:

Description

About the Program 

Programmable Logic Design has become a core technology utilized in building electronic systems.  By integrating soft-core or hardcore processors, these devices have evolved to complete systems on a chip, steadily augmenting or even displacing general purpose processors.  In particular, high performance computing is mostly archived with FPGAs.

This Workshop  is intended to give  participants a quick start and hands on practice needed for implementing  cutting edge projects especially in domains like  VLSI, Embedded Systems, Computer Architecture, Communication, DSP, Control and automation  Biomedical etc., targeting FPGA /ASIC.

  • Who should attend?  :  Engineering students, recent graduates and young professionals with back ground in Digital Electronics 
  • Duration: 65 Hours (Theory: 13 hours & Lab : 52 hours) 
  • 24X7 Self-paced using Recorded Lectures 
  • Certificate Criteria: 50 % for assignments and 50 % for exit test
  • Contents: Lectures, demos, Lab experiments and Mini project
  • Mode of Delivery: Theory sessions shall be delivered through online mode using recorded lectures by NPTEL. Lab demo (recorded) and live sessions shall be delivered through online mode by NIELIT Calicut. Lab experiments and Mini Project shall be done through the Remote SMART lab at NIELIT Calicut.

Major topics:

  • Introduction to VLSI Design flow 
  • RTL Design (Verilog HDL) Quick start
  • FSM Coding 
  • Fundamental of Programmable Logic
  • FPGA Architecture 
  • FPGA Design Flow 
  • Timing Fundamentals
  • Advanced FPGA Topics
  • FPGA based SoC Design-Case study