Description
About the Program
Module Duration: 65 Hours (13 hours theory and 52 hours lab)
Objective : The objective of the course is to provide a thorough theoretical understanding and practice with ARM based SoC design and simulation of peripherals using EDA tools.
This Workshop is intended to give participants a quick start and hands on practice needed for implementing cutting edge projects especially in domains like VLSI, Embedded Systems, Computer Architecture, Communication, DSP, Control and automation Biomedical etc., targeting FPGA /ASIC.
- Duration: 65 Hours (Theory: 13 hours & Lab : 52 hours)
- 24X7 Self-paced using Recorded Lectures
- Certificate Criteria: 50 % for assignments and 50 % for exit test
- Contents: Lectures, demos, Lab experiments and Mini project
- Mode of Delivery: Theory sessions shall be delivered through online mode using recorded lectures by NPTEL. Lab demo (recorded) and live sessions shall be delivered through online mode by NIELIT Calicut. Lab experiments and Mini Project shall be done using resources at participant’s computer using Freeware Tools/Evaluation Version of Industry standard EDA Tools.
Major topics:
- Introduction to Verilog HDL & Hierarchical Modelling Concepts
- AHB Light bus architecture
- Building a System on Chip- Integrating AHB peripherals to ARM
- UART, Timer, MEMORY, GPIO etc.
Profile of the instructor(s)
Dr. Jayaraj U Kidav
Scientist ‘D’, NIELIT Calicut
Educational Qualifications:
PhD (ECE) Specialized in VLSI Signal Processing.
M.E (ECE) Specialized in VLSI Design
Experience
R&D EXPERIENCE: 20+Years
Position and Organization
Scientist, NIELIT Calicut ( Electronic System Engineering, VLSI/ASIC/IPCore Design, Training) – 11 years
R & D Engineer, IBM India Pvt Ltd.,Systems & Technology Group, VLSI Processor Division (FPGA Emulation/Prototyping, RISC CPU Core modules design and development) – 3 years
Scientist, Defence R&D Organization (NPOL Cochin), Signal Processing Systems Division (Signal Processing Hardware and Software Development) – 5 years
AWARDS
- Received DRDO (NPOL) Award for Developing Parallel Processing DSP Hardware
- Received IBM award for Developing SoC FPGA Emulation platform
R & D Labs Established at NIELIT Calicut
- Advanced VLSI System Design Lab
- Funded R & D Lab for Medical Ultrasound research
- Chip to System Design Lab
- Swadeshi Microprocessor-based Remote Embedded System Design Lab
- Skilled Manpower Advance Research and Training (SMART) Facility
Nandakumar.R
Scientist ‘D’, NIELIT Calicut
Educational Qualifications:
M.E (ECE)
MBA
Experience
Total EXPERIENCE: 15 Years
Position and organization
Scientist, NIELIT Calicut, Electronic System Engineering, VLSI/ASIC/IPCore Design, Training
Adhoc Faculty, NIT Calicut
AWARDS
- IEEE Outstanding Young Professional Award (R10-Asia Pacific) 2015
R & D Labs Co-Established at NIELIT Calicut
- Advanced VLSI System Design Lab
- Chip to System Design Lab
- Swadeshi Microprocessor-based Remote Embedded System Design Lab
- Skilled Manpower Advance Research and Training (SMART) Facility
Sreejeesh SG
Senior Technical Officer, NIELIT Calicut
Educational Qualifications:
M.Tech (By Research)
B.Tech (ECE)
R&D EXPERIENCE: 15+Years
Position and Organization
Senior Technical Officer, NIELIT Calicut (VLSI/FPGA/ASIC/IPCore Design, Training) – 15 years.
R & D Labs Co-Established at NIELIT Calicut
- Advanced VLSI System Design Lab
- Funded R & D Lab for Medical Ultrasound research
- Chip to System Design Lab
- Swadeshi Microprocessor-based Remote Embedded System Design Lab
- Skilled Manpower Advance Research and Training (SMART) Facility
Registration and payment
Course Fee : Rs 2500/-
Payment link : https://rzp.io/l/MoGT4HD
Eligibility
Target Audience: BE/B.Tech (ECE/EEE/AEI/CSE/IT/Biomedical/Medical Electronics, Mechatronics and allied branches) / M.Sc. (Electronics/CS) or Ongoing with 3rd semester completed.
Who should attend? : Engineering students, recent graduates and young professionals with back ground in Digital Electronics
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