Description
About the Program
The future scope of VLSI engineers is very high as the world is full of electronics devices that consist of microcontrollers, microprocessors, etc. To design these chips or integrated circuits the VLSI engineers are required. Over the years there has been an increased demand for skilled VLSI engineers at IC design companies. This is due to the tremendous advances in AI, EV, and smartphone technologies, all of which rely on smart ICs. Chip design and manufacturing are collectively called VLSI design where VLSI stands for Very-Large-Scale-Integration.
The objective of the course is to give students solid introductory knowledge on VLSI design and the application of these concepts. This course is expected to be a very comprehensive supplement to course on Analog Circuits and can be instrumental in stimulating interest and developing aptitude among the participants. Open source simulation platforms like PSPICE or LT-SPICE will be used, so that all participants can carry out the simulations described in the course. This course can be very useful for UG as well as PG students, along with research scholars in the initial phases of their PhD study and course work.
Major topics:
- Introduction to VLSI Design Flow: Front end and Back-end
- CMOS transistor Theory, CMOS inverter characteristics,
- CMOS Logic Design, Transistor level schematics and layouts
- On chip wire modelling.
- Bonding diagram, packaging and assembly
- Gate Delays and Logical effort,
- Usage of P/N ratio to determine the best delay/power trade-off for logic gates
- Combinational logic circuit critical path optimization
- Timing in sequential circuits
Duration: 65 Hours (Theory: 13 hours & Lab : 52 hours) 24X7 Self-paced using Recorded Lectures
Certificate Criteria: 50 % for assignments and 50 % for exit test
Contents: Lectures, demos, Lab experiments and Mini project
Mode of Delivery: Theory sessions shall be delivered through online mode using recorded lectures by NPTEL. Lab demo (recorded) and live sessions (if any) shall be delivered through online mode by NIELIT Calicut.
Lab experiments and Mini Project shall be done through the using open source downloadable tools.
For more details on the workshop or for any queries, please contact
Shri. Nandakumar, S/E “D” – Mobile: 9995427802 email : nanda@calicut.nielit.in
Shri Sreejeesh SG , STO Mobile : 9447769756 email: sree@calicut.nielit.in
Profile of the instructor(s)
Dr. Jayaraj U Kidav
Scientist ‘D’, NIELIT Calicut
Educational Qualifications:
PhD (ECE) Specialized in VLSI Signal Processing.
M.E (ECE) Specialized in VLSI Design
Experience
R&D EXPERIENCE: 20+Years
Position and Organization
Scientist, NIELIT Calicut ( Electronic System Engineering, VLSI/ASIC/IPCore Design, Training) – 11 years
R & D Engineer, IBM India Pvt Ltd.,Systems & Technology Group, VLSI Processor Division (FPGA Emulation/Prototyping, RISC CPU Core modules design and development) – 3 years
Scientist, Defence R&D Organization (NPOL Cochin), Signal Processing Systems Division (Signal Processing Hardware and Software Development) – 5 years
AWARDS
- Received DRDO (NPOL) Award for Developing Parallel Processing DSP Hardware
- Received IBM award for Developing SoC FPGA Emulation platform
R & D Labs Established at NIELIT Calicut
- Advanced VLSI System Design Lab
- Funded R & D Lab for Medical Ultrasound research
- Chip to System Design Lab
- Swadeshi Microprocessor-based Remote Embedded System Design Lab
- Skilled Manpower Advance Research and Training (SMART) Facility
Nandakumar.R
Scientist ‘D’, NIELIT Calicut
Educational Qualifications:
M.E (ECE)
MBA
Experience
Total EXPERIENCE: 15 Years
Position and organization
Scientist, NIELIT Calicut, Electronic System Engineering, VLSI/ASIC/IPCore Design, Training
Adhoc Faculty, NIT Calicut
AWARDS
- IEEE Outstanding Young Professional Award (R10-Asia Pacific) 2015
R & D Labs Co-Established at NIELIT Calicut
- Advanced VLSI System Design Lab
- Chip to System Design Lab
- Swadeshi Microprocessor-based Remote Embedded System Design Lab
- Skilled Manpower Advance Research and Training (SMART) Facility
Sreejeesh SG
Senior Technical Officer, NIELIT Calicut
Educational Qualifications:
M.Tech (By Research)
B.Tech (ECE)
R&D EXPERIENCE: 15+Years
Position and Organization
Senior Technical Officer, NIELIT Calicut (VLSI/FPGA/ASIC/IPCore Design, Training) – 15 years.
R & D Labs Co-Established at NIELIT Calicut
- Advanced VLSI System Design Lab
- Funded R & D Lab for Medical Ultrasound research
- Chip to System Design Lab
- Swadeshi Microprocessor-based Remote Embedded System Design Lab
- Skilled Manpower Advance Research and Training (SMART) Facility
Registration and payment
Registration fee Rs.2500
Register and pay using the following link:
https://pages.razorpay.com/pl_L7bQDV6wM1XSRN/view
Eligibility
Engineering students, recent graduates and young professionals with back ground in Digital Electronics
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