Lab Workshop Advanced ARM SoC Design

SKU: Start Date: February 26, 2024 Category:

Description

The objective of the course is to provide a thorough theoretical understanding and practice with ARM based SoC design and Synthesis of peripherals using EDA tools.

 

Session Date : 26th February, 2024

 

Duration : 65 Hours (Theory : 13 hours & Lab : 52 hours)

 

Profile of the Instructor(s)

Mr. Nandakumar.R

Scientist ‘D’, NIELIT Calicut

 

Educational Qualifications:

M.E (ECE) , MBA

 

Experience : 15 Years

 

Position and Organization:

Scientist, NIELIT Calicut, Electronic System Engineering, VLSI/ASIC/IPCore Design, Training

Adhoc Faculty, NIT Calicut

 

AWARDS:

  1. IEEE Outstanding Young Professional Award (R10-Asia Pacific) 2015

 

R & D Labs Co-Established at NIELIT Calicut

  1. Advanced VLSI System Design Lab
  2. Chip to System Design Lab
  3. Swadeshi Microprocessor-based Remote Embedded System Design Lab
  4. Skilled Manpower Advance Research and Training (SMART) Facility

 

Mr Sreejeesh SG

Senior Technical Officer, NIELIT Calicut

 

Educational Qualifications:

M.Tech (By Research) , B.Tech (ECE)

 

R&D EXPERIENCE: 15+Years 

 

Position and Organization:

Senior Technical Officer, NIELIT Calicut (VLSI/FPGA/ASIC/IPCore Design, Training) – 15 years.

 

R & D Labs Co-Established at NIELIT Calicut

  1. Advanced VLSI System Design Lab
  2. Funded R & D Lab for Medical Ultrasound research
  3. Chip to System Design Lab
  4. Swadeshi Microprocessor-based Remote Embedded System Design Lab
  5. Skilled Manpower Advance Research and Training (SMART) Facility

Topics Covered

 

  1. Fundamental of Programmable Logic
  2. FPGA Architecture
  3. FPGA Design Flow
  4. ARM M0 Architecture
  5. AHB Light bus architecture
  6. Assembly Programing for ARM
  7. ARM M1 & M3 Architecture
  8. Building a System on Chip- Integrating AHB peripherals to ARM using Verilog HD for UART, Timer, MEMORY, GPIO etc.
  9. Synthesis of AHB peripherals on the ARTY A7 FPGA Kits
  10. Synthesis of UART, Timer, MEMORY, GPIO etc.
  11. ZYNQ Architecture and Demo of ZYNQ Programming.

Intended Audience

Engineering students, recent graduates and young professionals with back ground in Digital Electronics.

BE/B.Tech (ECE/EEE/AEI/CSE/IT/Biomedical/Medical Electronics, Mechatronics and allied branches) / M.Sc. (Electronics/CS) or Ongoing with 3rd semester completed.

This Workshop is intended to give participants a quick start and hands on practice needed for implementing cutting edge projects especially in domains like VLSI, Embedded Systems, Computer Architecture, Communication, DSP, Control and automation Biomedical etc., targeting FPGA /ASIC.

Perquisites for the program

Verilog HDL Knowledge / Lab Workshop on FPGA Architecture and Programming using Verilog HDL /Lab Workshop on ARM Based SoC Design.

Certification

50 % for assignments and 50 % for exit test

Mode of Delivery

Theory sessions shall be delivered through ONLINE mode using recorded lectures by NPTEL.

Lab demo (recorded) and live sessions (if any) shall be delivered through ONLINE mode by NIELIT Calicut.

 

Lab experiments and Mini Project shall be done using resources at participant’s computer using Freeware Tools/Evaluation Version of Industry standard EDA Tools or in our Remote Hardware Lab.

Registration

Selection will be based on ‘first come first serve basis’ among eligible registrants. Registration will be closed once sufficient number of candidates for a batch has registered.

Welcome mail will be sent by NIELIT Calicut to their registered email a day prior to start day of the course.

 

Registration Link :

https://pages.razorpay.com/pl_MkT353aG6CH7ZE/view

Support Desk

Workshop Coordinator: 

Name : R. Nandakumar

Phone : 9995427802

Mail ID : nanda@nielit.gov.in, nanda@calicut.nielit.in

 

 

For Queries/Support : 

Name : S.G Sreejeesh

Phone : 9447769756

Mail ID : sreejeesh@nielit.gov.in, sree@calicut.nielit.in

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