Description
The objective of the course is to provide a thorough theoretical understanding and practice with ARM based SoC design and Synthesis of peripherals using EDA tools.
Session Date : 26th February, 2024
Duration : 65 Hours (Theory : 13 hours & Lab : 52 hours)
Profile of the Instructor(s)
Mr. Nandakumar.R
Scientist ‘D’, NIELIT Calicut
Educational Qualifications:
M.E (ECE) , MBA
Experience : 15 Years
Position and Organization:
Scientist, NIELIT Calicut, Electronic System Engineering, VLSI/ASIC/IPCore Design, Training
Adhoc Faculty, NIT Calicut
AWARDS:
- IEEE Outstanding Young Professional Award (R10-Asia Pacific) 2015
R & D Labs Co-Established at NIELIT Calicut
- Advanced VLSI System Design Lab
- Chip to System Design Lab
- Swadeshi Microprocessor-based Remote Embedded System Design Lab
- Skilled Manpower Advance Research and Training (SMART) Facility
Mr Sreejeesh SG
Senior Technical Officer, NIELIT Calicut
Educational Qualifications:
M.Tech (By Research) , B.Tech (ECE)
R&D EXPERIENCE: 15+Years
Position and Organization:
Senior Technical Officer, NIELIT Calicut (VLSI/FPGA/ASIC/IPCore Design, Training) – 15 years.
R & D Labs Co-Established at NIELIT Calicut
- Advanced VLSI System Design Lab
- Funded R & D Lab for Medical Ultrasound research
- Chip to System Design Lab
- Swadeshi Microprocessor-based Remote Embedded System Design Lab
- Skilled Manpower Advance Research and Training (SMART) Facility
Intended Audience
Engineering students, recent graduates and young professionals with back ground in Digital Electronics.
BE/B.Tech (ECE/EEE/AEI/CSE/IT/Biomedical/Medical Electronics, Mechatronics and allied branches) / M.Sc. (Electronics/CS) or Ongoing with 3rd semester completed.
This Workshop is intended to give participants a quick start and hands on practice needed for implementing cutting edge projects especially in domains like VLSI, Embedded Systems, Computer Architecture, Communication, DSP, Control and automation Biomedical etc., targeting FPGA /ASIC.
Perquisites for the program
Verilog HDL Knowledge / Lab Workshop on FPGA Architecture and Programming using Verilog HDL /Lab Workshop on ARM Based SoC Design.
Mode of Delivery
Theory sessions shall be delivered through ONLINE mode using recorded lectures by NPTEL.
Lab demo (recorded) and live sessions (if any) shall be delivered through ONLINE mode by NIELIT Calicut.
Lab experiments and Mini Project shall be done using resources at participant’s computer using Freeware Tools/Evaluation Version of Industry standard EDA Tools or in our Remote Hardware Lab.
Registration
Selection will be based on ‘first come first serve basis’ among eligible registrants. Registration will be closed once sufficient number of candidates for a batch has registered.
Welcome mail will be sent by NIELIT Calicut to their registered email a day prior to start day of the course.
Registration Link :
https://pages.razorpay.com/pl_MkT353aG6CH7ZE/view
Support Desk
Workshop Coordinator:
Name : R. Nandakumar
Phone : 9995427802
Mail ID : nanda@nielit.gov.in, nanda@calicut.nielit.in
For Queries/Support :
Name : S.G Sreejeesh
Phone : 9447769756
Mail ID : sreejeesh@nielit.gov.in, sree@calicut.nielit.in
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