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Lab Workshop ‘FPGA Architecture and Programming using Verilog HDL

(3 customer reviews)

SKU: NIELIT WORKSHOP | Starts on April 4th, 2022 Category:

Description

About the Program 

Programmable Logic Design has become a core technology utilized in building electronic systems.  By integrating soft-core or hardcore processors, these devices have evolved to complete systems on a chip, steadily augmenting or even displacing general purpose processors.  In particular, high performance computing is mostly archived with FPGAs.

This Workshop  is intended to give  participants a quick start and hands on practice needed for implementing  cutting edge projects especially in domains like  VLSI, Embedded Systems, Computer Architecture, Communication, DSP, Control and automation  Biomedical etc., targeting FPGA /ASIC.

  • Who should attend?  :  Engineering students, recent graduates and young professionals with back ground in Digital Electronics 
  • Duration: 65 Hours (Theory: 13 hours & Lab : 52 hours) 
  • 24X7 Self-paced using Recorded Lectures 
  • Certificate Criteria: 50 % for assignments and 50 % for exit test
  • Contents: Lectures, demos, Lab experiments and Mini project
  • Mode of Delivery: Theory sessions shall be delivered through online mode using recorded lectures by NPTEL. Lab demo (recorded) and live sessions shall be delivered through online mode by NIELIT Calicut. Lab experiments and Mini Project shall be done through the Remote SMART lab at NIELIT Calicut.

Major topics:

  • Introduction to VLSI Design flow 
  • RTL Design (Verilog HDL) Quick start
  • FSM Coding 
  • Fundamental of Programmable Logic
  • FPGA Architecture 
  • FPGA Design Flow 
  • Timing Fundamentals
  • Advanced FPGA Topics
  • FPGA based SoC Design-Case study

Profile of the instructor(s)

Dr. Jayaraj U Kidav Scientist 'D', NIELIT Calicut Educational Qualifications: PhD (ECE) Specialized in VLSI Signal Processing. M.E (ECE) Specialized in VLSI Design Experience R&D EXPERIENCE: 20+Years Position and Organization Scientist, NIELIT Calicut ( Electronic System Engineering, VLSI/ASIC/IPCore Design, Training) - 11 years R & D Engineer, IBM India Pvt Ltd.,Systems & Technology Group, VLSI Processor Division (FPGA Emulation/Prototyping, RISC CPU Core modules design and development) - 3 years Scientist, Defence R&D Organization (NPOL Cochin),  Signal Processing Systems Division (Signal Processing Hardware and Software Development) - 5 years AWARDS
  1. Received DRDO (NPOL) Award for Developing Parallel Processing DSP Hardware
  2. Received IBM award for Developing SoC FPGA Emulation platform
R & D Labs Established at NIELIT Calicut
  1. Advanced VLSI System Design Lab
  2. Funded R & D Lab for Medical Ultrasound research
  3. Chip to System Design Lab
  4. Swadeshi Microprocessor-based Remote Embedded System Design Lab
  5. Skilled Manpower Advance Research and Training (SMART) Facility
Nandakumar.R Scientist 'D', NIELIT Calicut Educational Qualifications: M.E (ECE)  MBA Experience Total  EXPERIENCE: 15 Years Position and organization Scientist, NIELIT Calicut, Electronic System Engineering, VLSI/ASIC/IPCore Design, Training Adhoc Faculty, NIT Calicut AWARDS
  1. IEEE Outstanding Young Professional Award (R10-Asia Pacific) 2015
R & D Labs Co-Established at NIELIT Calicut
  1. Advanced VLSI System Design Lab
  2. Chip to System Design Lab
  3. Swadeshi Microprocessor-based Remote Embedded System Design Lab
  4. Skilled Manpower Advance Research and Training (SMART) Facility
Sreejeesh SG Senior Technical Officer, NIELIT Calicut Educational Qualifications: M.Tech (By Research) B.Tech (ECE)  R&D EXPERIENCE: 15+Years  Position and Organization Senior Technical Officer, NIELIT Calicut (VLSI/FPGA/ASIC/IPCore Design, Training) – 15 years. R & D Labs Co-Established at NIELIT Calicut
  1. Advanced VLSI System Design Lab
  2. Funded R & D Lab for Medical Ultrasound research
  3. Chip to System Design Lab
  4. Swadeshi Microprocessor-based Remote Embedded System Design Lab
  5. Skilled Manpower Advance Research and Training (SMART) Facility
 

Registration and payment

Registration fee Rs.2000 Register and pay using the following link https://pages.razorpay.com/pl_J5IBc45VODQOWK/view

3 reviews for Lab Workshop ‘FPGA Architecture and Programming using Verilog HDL

  1. K SELVAM, Assistant Professor, Department of Tourism & Hospitality Management, Annai Fathima College of Arts & Science, Email: selvam.k.2007@gmail.com –

    It is useful and it’s informative program

  2. Sunil Gaikwad –

    FPGA Lab workshop was Informative and very useful for beginners.

  3. S.Navya Deepika –

    This workshop is very useful for beginners to improve their skills in the VLSI domain.

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