Digital System Design and Testing

Digital System Design and Testing

Last Date of Registration : 25th June, 2025

This product is currently out of stock and unavailable.

SKU: IIT Bombay : Dates - June 30 – July 04, 2025 Category:

Details of the Short Term Program

Digital System Design and Testing [focused on Hardware Description Language specifically VHDL simulation and synthesis]  Getting started videos to set the background for VHDL and study material will be made available 3-4 days in advance 
  • Quartus Installation Guide
  • Using Quartus for project generation and simulation
  • Introduction to VHDL by Prof. Dinesh Sharma 
  • Structural Description by Prof. Dinesh Sharma 
  • Structural description of Full Adder by Prof. Dinesh Sharma 
  • Full Adder Testbench by Prof. Dinesh Sharma
  • Full Adder Demo Resources 
Suggested Reference Books:
  • A VHDL Primer by J. Bhasker
  • Digital Logic and Computer Design by M. Morris Mano
  • VHDL_by_Peter_J_Ashenden

Profile of the Instructors

Dr. Siddharth Tallur Dr. Siddharth Tallur is an Associate Professor at the Department of Electrical Engineering, IIT Bombay and faculty-in-charge of Wadhwani Electronics Lab (WEL) at IIT Bombay. Prior to joining IIT Bombay, he worked at Analog Devices Inc. Wilmington MA, USA on MEMS sensor product and applications development. His current research interests include high resolution and low-cost sensors, high speed instrumentation and embedded systems for sensing applications, most notably for structural health monitoring and biosensing Mr. Mahesh The workshop will be conducted and logistically managed by Mr. Mahesh Bhaganagare (Asst. Technical Officer, WEL), the Wadhwani Electronics lab staff and the Research Assistants (RAs)/ Research Scholars (PhD students)

Schedule of the Short term Program

         
  • Assignment to be submitted at 5.30 pm for the assessment
  • Assignment to be submitted at 3.30 pm for the assessment
  • Quiz time: 4 pm to 5 pm

Fee Structure

Student : Rs 1770 /- (1500 + 18% GST )

Faculty : Rs 2950 /- (2500 + 18% GST )

Industry : Rs 3540 /- (3000 + 18% GST )

Session Details

Dates of the Workshop : June 30 - July 04, 2025 (Monday - Friday)

Mode of the Workshop : Online

Timings (on all days)

Morning (FN) : 09:30 am to 12:30 pm (IST)

Afternoon(AN) : 02:00 pm to 05:00 pm (IST)

   

Intended Audience & Eligibility

Intended Audience

  • Students (Undergrad, Postgrad, PhD), Faculty, Industry Professionals interested in learning the Digital Design, implementation and verification concepts in hardware description language specifically VHDL

Eligibility Criteria

Familiarity with Digital Circuit Design is essential [UG level, 2nd year/3rd year]  

Certification Criteria

Attendance, Daily Assignment submissions and Quiz performance will be considered for certification.
  • The daily schedule will commence with a review of the solutions to the assignment(s) from the previous day.
  • Subsequently, a new assignment will be issued and the problem statement will be discussed.
  • A quiz will be conducted towards the conclusion of the course followed by a discussion of the solutions. Each participant will receive feedback in terms of score.

Reviews

There are no reviews yet.

Be the first to review “Digital System Design and Testing”