Workshop on FPGA Architecture and Programming using Verilog HDL - Batch 8

Workshop on FPGA Architecture and Programming using Verilog HDL – Batch 8

SKU: Start Date:October 14, 2024 Category:

Description

Programmable Logic Design has become a core technology utilized in building electronic systems.  By integrating soft-core or hardcore processors, these devices have evolved to complete systems on a chip, steadily augmenting or even displacing general purpose processors.  In particular, high performance computing is mostly archived with FPGAs.

This Workshop  is intended to give  participants a quick start and hands on practice needed for implementing  cutting edge projects especially in domains like  VLSI, Embedded Systems, Computer Architecture, Communication, DSP, Control and automation  Biomedical etc., targeting FPGA /ASIC.

 

Session Date: 14th October, 2024

 

Duration : 65 Hours (Theory: 13 hours & Lab : 52 hours)

 

Topics Covered

  1. Introduction to VLSI Design flow 
  2. RTL Design (Verilog HDL) Quick start
  3. FSM Coding 
  4. Fundamental of Programmable Logic
  5. FPGA Architecture 
  6. FPGA Design Flow 
  7. Timing Fundamentals
  8. Advanced FPGA Topics
  9. FPGA based SoC Design-Case study

Intended Audience

Engineering students, recent graduates and young professionals with Basic knowledge of any programming language (Preferably C) is recommended.

Certification

50 % for assignments and 50 % for exit test

Mode of Delivery

Theory sessions shall be delivered through ONLINE mode using recorded lectures by NPTEL. Lab demo (recorded) and live sessions (if any) shall be delivered through ONLINE mode by NIELIT Calicut.   Lab experiments and Mini Project shall be done through Open source/ Licence free tools.

Registration

Selection will be based on 'first come first serve basis' among eligible registrants. Registration will be closed once sufficient number of candidates for a batch has registered.

Welcome mail will be sent by NIELIT Calicut to their registered email a day prior to start day of the course.

 

Registration Link :

https://rzp.io/l/Mbib26g

Support Desk

Workshop Coordinator: 

Name : R. Nandakumar Phone : 9995427802 Mail ID : nanda@nielit.gov.in, nanda@calicut.nielit.in    

For Queries/Support : 

Name : S.G Sreejeesh Phone : 9447769756 Mail ID : sreejeesh@nielit.gov.in, sree@calicut.nielit.in

Profile of the Instructor

Dr. Jayaraj U Kidav Scientist 'G', NIELIT Aurangabad  

Educational Qualifications:

PhD (ECE) Specialized in VLSI Signal Processing. M.E (ECE) Specialized in VLSI Design

Experience:

R&D EXPERIENCE: 20+Years  

Position and Organization

Scientist, NIELIT Calicut ( Electronic System Engineering, VLSI/ASIC/IPCore Design, Training) - 11 years R & D Engineer, IBM India Pvt Ltd.,Systems & Technology Group, VLSI Processor Division (FPGA Emulation/Prototyping, RISC CPU Core modules design and development) - 3 years Scientist, Defence R&D Organization (NPOL Cochin),  Signal Processing Systems Division (Signal Processing Hardware and Software Development) - 5 years  

AWARDS

  1. Received DRDO (NPOL) Award for Developing Parallel Processing DSP Hardware
  2. Received IBM award for Developing SoC FPGA Emulation platform
 

R & D Labs Established at NIELIT Calicut

  1. Advanced VLSI System Design Lab
  2. Funded R & D Lab for Medical Ultrasound research
  3. Chip to System Design Lab
  4. Swadeshi Microprocessor-based Remote Embedded System Design Lab
  5. Skilled Manpower Advance Research and Training (SMART) Facility
  2. Nandakumar.R Scientist 'D', NIELIT Calicut  

Educational Qualifications:

M.E (ECE) , MBA  

Experience:

Total  EXPERIENCE: 15 Years  

Position and organization:

Scientist, NIELIT Calicut, Electronic System Engineering, VLSI/ASIC/IPCore Design, Training Adhoc Faculty, NIT Calicut  

AWARDS:

  1. IEEE Outstanding Young Professional Award (R10-Asia Pacific) 2015
  R & D Labs Co-Established at NIELIT Calicut
  1. Advanced VLSI System Design Lab
  2. Chip to System Design Lab
  3. Swadeshi Microprocessor-based Remote Embedded System Design Lab
  4. Skilled Manpower Advance Research and Training (SMART) Facility
 

3. Sreejeesh SG

Senior Technical Officer, NIELIT Calicut

 

Educational Qualifications:

M.Tech (By Research) , B.Tech (ECE)   

R&D EXPERIENCE: 15+Years 

Position and Organization Senior Technical Officer, NIELIT Calicut (VLSI/FPGA/ASIC/IPCore Design, Training) – 15 years.   R & D Labs Co-Established at NIELIT Calicut
  1. Advanced VLSI System Design Lab
  2. Funded R & D Lab for Medical Ultrasound research
  3. Chip to System Design Lab
  4. Swadeshi Microprocessor-based Remote Embedded System Design Lab
  5. Skilled Manpower Advance Research and Training (SMART) Facility

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