Advanced ARM SoCs Design - Batch 1

Advanced ARM SoCs Design – Batch 1

Session Date : 27th November, 2023

 

Register through the link given under the Registration & Payment Tab

 

SKU: NIELIT WORKSHOP | Starts on 27th November 2023 Category:

Description

Objective:

The objective of the course is to provide a thorough theoretical understanding and practice with ARM based SoC design and Synthesis of peripherals using EDA tools.

 

About the Program:

24X7 Self-paced using Recorded Lectures.

 

Mode of Delivery:

Theory sessions shall be delivered through online mode using recorded lectures by NPTEL. Lab demo (recorded) and live sessions shall be delivered through online mode by NIELIT Calicut. Lab experiments and Mini Project shall be done using resources at participant’s computer using Freeware Tools/Evaluation Version of Industry standard EDA Tools or in our Remote Hardware Lab

Topics Covered

  • Fundamental of Programmable Logic
  • FPGA Architecture
  • FPGA Design Flow
  • ARM M0 Architecture
  • AHB Light bus architecture
  • Assembly Programing for ARM
  • ARM M1 & M3 Architecture
  • Building a System on Chip- Integrating AHB peripherals to ARM using Verilog HD for UART, Timer, MEMORY, GPIO etc.
  • Synthesis of AHB peripherals on the ARTY A7 FPGA Kits
  • Synthesis of UART, Timer, MEMORY, GPIO etc.
  • ZYNQ Architecture and Demo of ZYNQ Programming.

Profile of the instructor(s)

Mr. Nandakumar.R

Scientist 'D', NIELIT Calicut.  

Educational Qualifications:

M.E (ECE) , MBA  

Experience: 15 Years

 

Position and Organization:

Scientist, NIELIT Calicut, Electronic System Engineering, VLSI/ASIC/IPCore Design, Training Adhoc Faculty, NIT Calicut  

AWARDS:

  1. IEEE Outstanding Young Professional Award (R10-Asia Pacific) 2015
R & D Labs Co-Established at NIELIT Calicut
  1. Advanced VLSI System Design Lab
  2. Chip to System Design Lab
  3. Swadeshi Microprocessor-based Remote Embedded System Design Lab
  4. Skilled Manpower Advance Research and Training (SMART) Facility
 

Mr. Sreejeesh SG

Senior Technical Officer, NIELIT Calicut  

Educational Qualifications:

M.Tech (By Research), B.Tech (ECE)   

R&D EXPERIENCE: 15+Years 

 

Position and Organization:

Senior Technical Officer, NIELIT Calicut (VLSI/FPGA/ASIC/IPCore Design, Training) – 15 years.  

R & D Labs Co-Established at NIELIT Calicut

  1. Advanced VLSI System Design Lab
  2. Funded R & D Lab for Medical Ultrasound research
  3. Chip to System Design Lab
  4. Swadeshi Microprocessor-based Remote Embedded System Design Lab
  5. Skilled Manpower Advance Research and Training (SMART) Facility

Pre - Requisite

Verilog HDL Knowledge / Lab Workshop on FPGA Architecture and Programming using Verilog HDL /Lab Workshop on ARM Based SoC Design.

Intended Audience

BE/B.Tech (ECE/EEE/AEI/CSE/IT/Biomedical/Medical Electronics, Mechatronics and allied branches) / M.Sc. (Electronics/CS) or Ongoing with 3rd semester completed.

This Workshop is intended to give participants a quick start and hands on practice needed for implementing cutting edge projects especially in domains like VLSI, Embedded Systems, Computer Architecture, Communication, DSP, Control and automation Biomedical etc., targeting FPGA /ASIC.

Dates to be noted

Event

Date

Registration Closes on

First Come First Serve Basis

Sharing of Course link

26th November, 2023

Course Start date

27th November, 2023

Course Duration

65 Hours (13 hours theory and 52 hours lab)

Registration and Payment

Registration fee : Rs.2500   Register and pay using the following link: https://pages.razorpay.com/pl_MukqeK5bbaLbGh/view

Eligibility & Certification

Engineering students, recent graduates and young professionals with back ground in Digital Electronics.    

Certification:

50 % for assignments and 50 % for exit test

FAQs

https://www.nielit.gov.in/calicut/sites/default/files/course/FAQAdvancedARM.pdf

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