Workshop on VLSI Fundamentals

SKU: Start Date: December 4, 2023 Category:

Description

The future scope of VLSI engineers is very high as the world is full of electronics devices that consist of microcontrollers, microprocessors, etc. To design these chips or integrated circuits the VLSI engineers are required. Over the years there has been an increased demand for skilled VLSI engineers at IC design companies. This is due to the tremendous advances in AI, EV and smartphone technologies, all of which rely on smart ICs. Chip design and manufacturing are collectively called VLSI design where VLSI stands for Very-Large-Scale-Integration.

The objective of the course is to give students solid introductory knowledge on VLSI design and the application of these concepts. This course is expected to be a very comprehensive supplement to course on Analog Circuits and can be instrumental in stimulating interest and developing aptitude among the participants. Open source simulation platforms like PSPICE or LT-SPICE will be used, so that all participants can carry out the simulations described in the course. This course can be very useful for UG as well as PG students, along with research scholars in the initial phases of their PhD study and course work.

 

Session Date: 4th December, 2023

 

Duration : 65 Hours (Theory: 13 hours & Lab : 52 hours)

 

Topics Covered

  1. Introduction to VLSI Design Flow: Front end and Back-end
  2. CMOS transistor Theory, CMOS inverter characteristics,
  3. CMOS Logic Design, Transistor level schematics and layouts
  4. On chip wire modelling.
  5. Bonding diagram, packaging and assembly
  6. Gate Delays and Logical effort,
  7. Usage of P/N ratio to determine the best delay/power trade-off for logic gates
  8. Combinational logic circuit critical path optimization
  9. Timing in sequential circuits

Intended Audience

Engineering students, recent graduates and young professionals with back ground in Digital Electronics

Certification

50 % for assignments and 50 % for exit test

Mode of Delivery

Theory sessions shall be delivered through ONLINE mode using recorded lectures by NPTEL.

Lab demo (recorded) and live sessions (if any) shall be delivered through ONLINE mode by NIELIT Calicut.

Lab experiments and Mini Project shall be done through Open source/ Licence free tools.

Registration

Selection will be based on ‘first come first serve basis’ among eligible registrants. Registration will be closed once sufficient number of candidates for a batch has registered.

Welcome mail will be sent by NIELIT Calicut to their registered email a day prior to start day of the course.

Registration Link :

https://pages.razorpay.com/pl_MkT353aG6CH7ZE/view

Support Desk

Workshop Coordinators: 

Name: Nandakumar.R, Scientist ‘D’ .

Email : nanda@calicut.nielit.in

For Queries/Support : 

Name : Mr Sreejeesh, STO .

Email :sree@calicut.nielit.in, sreejeesh@nielit.gov.in.

Phone : 94477 69756

Profile of the Instructor(s)

Mr. Nandakumar.R

Scientist ‘D’, NIELIT Calicut

Educational Qualifications:

M.E (ECE) , MBA

Total  EXPERIENCE: 15 Years

Position and Organization: 

Scientist, NIELIT Calicut, Electronic System Engineering, VLSI/ASIC/IPCore Design, Training

Adhoc Faculty, NIT Calicut

AWARDS:

  1. IEEE Outstanding Young Professional Award (R10-Asia Pacific) 2015

R & D Labs Co-Established at NIELIT Calicut

  1. Advanced VLSI System Design Lab
  2. Chip to System Design Lab
  3. Swadeshi Microprocessor-based Remote Embedded System Design Lab
  4. Skilled Manpower Advance Research and Training (SMART) Facility

Mr. Sreejeesh SG

Senior Technical Officer, NIELIT Calicut

Educational Qualifications:

M.Tech (By Research), B.Tech (ECE)

R&D EXPERIENCE: 15+Years 

Position and Organization:

Senior Technical Officer, NIELIT Calicut (VLSI/FPGA/ASIC/IPCore Design, Training) – 15 years.

R & D Labs Co-Established at NIELIT Calicut

  1. Advanced VLSI System Design Lab
  2. Funded R & D Lab for Medical Ultrasound research
  3. Chip to System Design Lab
  4. Swadeshi Microprocessor-based Remote Embedded System Design Lab
  5. Skilled Manpower Advance Research and Training (SMART) Facility

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