This course will discuss the basic background of switching circuits, and discuss techniques for mapping the theory to actual hardware circuits. Synthesis and minimization techniques of combinational and sequential circuits shall be discussed in detail. Designing circuits using high-level functional blocks shall also be discussed. The course will closely follow the undergraduate curriculum existing in most engineering colleges.
Any Engineering Students/Faculty
Basic knowledge of electronics and electrical circuitsl
TCS, Wipro, CTS, Google, Microsoft, HP, Intel, IBM
ABOUT THE INSTRUCTOR
Indranil Sengupta has obtained his B.Tech., M.Tech. and Ph.D. degrees in Computer Science and Engineering from the University of Calcutta. He joined the Indian Institute of Technology, Kharagpur, as a faculty member in 1988, in the Department of Computer Science and Engineering, where he is presently a full Professor. He had been the former Heads of the Department of Computer Science and Engineering and also the School of Information Technology of the Institute. He has over 28 years of teaching and research experience. He has guided 22 PhD students, and has more than 200 publications to his credit in international journals and conferences. His research interests include cryptography and network security, VLSI design and testing, and mobile computing.
He is a Senior Member of IEEE. He had been the General Chairs of Asian Test Symposium (ATS-2005), International Conference on Cryptology in India (INDOCRYPT-2008), International Symposium on VLSI Design and Test (VDAT-2012), International Symposium on Electronic System Design (ISED-2012), and the upcoming Conference on reversible Computation (RC-2017). He had delivered invited and tutorial talks in several conferences in the areas of VLSI design and testing, and network security.
1. Join the course
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COURSE ENROLMENT FEE: The Fee for Enrolment is Rs. 3000 + GST
2. Watch Videos+Submit Assignments
After enrolling, learners can watch lectures and learn and follow it up with attempting/answering the assignments given.
3. Get qualified to register for exams
A learner can earn a certificate in the self paced course only by appearing for the online remote proctored exam and to register for this, the learner should get minimum required marks in the assignments as given below:
CRITERIA TO GET A CERTIFICATE
Assignment score = Score more than 50% in at least 9/12 assignments.
Exam score = 50% of the proctored certification exam score out of 100
Only the e-certificate will be made available. Hard copies will not be dispatched.”
4. Register for exams
The certification exam is conducted online with remote proctoring. Once a learner has become eligible to register for the certification exam, they can choose a slot convenient to them from what is available and pay the exam fee. Schedule of available slot dates/timings for these remote-proctored online examinations will be published and made available to the learners.
EXAM FEE: The remote proctoring exam is optional for a fee of Rs.1500 + GST. An additional fee of Rs.1500 will apply for a non-standard time slot.
5. Results and Certification
After the exam, based on the certification criteria of the course, results will be declared and learners will be notified of the same. A link to download the e-certificate will be shared with learners who pass the certification exam.
Week 1 : Introduction to number systems and codes, error detection and correction, binary arithmetic. Week 2 : Switching primitives and logic gates, logic families: TTL, CMOS, memristors, all-optical realizations. Week 3 : Boolean algebra: Boolean operations and functions, algebraic manipulation, minterms and maxterms, sum-of-products and product-of-sum representations, functional completeness. Week 4 : Minimization of Boolean functions: K-map method, prime implicants, don’t care conditions, Quine-McCluskey method, multi-level minimization. Week 5 : Design of combinational logic circuits: adders and subtractors, comparator, multiplexer, demultiplexer, encoder, etc. Week 6 : Representation of Boolean functions: binary decision diagram, Shannon’s decomposition, Reed-Muller canonical form, etc. Week 7 : Design of latches and flip-flops: SR, D, JK, T. Master-slave and edge-triggered flip-flops. Clocking and timing issues. Week 8 : Synthesis of synchronous sequential circuits, Mealy and Moore machines, state minimization. Week 9 : Design of registers, shift registers, ring counters, binary and BCD counters. General counter design methodology. Week 10: Algorithmic state machine and data/control path design. Week 11: Asynchronous sequential circuits: analysis and synthesis, minimization, static and dynamic hazards. Week 12: Testing and fault diagnosis in digital circuits: fault modeling, test generation and fault simulation, fault diagnosis, design for testability and built-in self-test.