Workshop on FPGA Architecture and Programming using Verilog HDL

SKU: Start Date: 9th June, 2025 Categories: ,

Description

Programmable Logic Design has become a core technology utilized in building electronic systems.  By integrating soft-core or hardcore processors, these devices have evolved to complete systems on a chip, steadily augmenting or even displacing general-purpose processors.  In particular, high-performance computing is mostly archived with FPGAs.

This Workshop  is intended to give participants a quick start and hands-on practice needed for implementing cutting-edge projects especially in domains like  VLSI, Embedded Systems, Computer Architecture, Communication, DSP, Control and automation  Biomedical, etc., targeting FPGA /ASIC.

 

Session Date: 9th June, 2025

 

Duration : 65 Hours (Theory: 13 hours & Lab : 52 hours)

 

Topics Covered

  1. Introduction to VLSI Design flow 
  2. RTL Design (Verilog HDL) Quick start
  3. FSM Coding 
  4. Fundamental of Programmable Logic
  5. FPGA Architecture 
  6. FPGA Design Flow 
  7. Timing Fundamentals
  8. Advanced FPGA Topics
  9. FPGA based SoC Design-Case study

Intended Audience

Engineering students, recent graduates and young professionals with Basic knowledge of any programming language (Preferably C) is recommended.

Certification

50 % for assignments and 50 % for exit test

Mode of Delivery

Theory sessions shall be delivered through ONLINE mode using recorded lectures by NPTEL.

Lab demo (recorded) and live sessions (if any) shall be delivered through ONLINE mode by NIELIT Calicut.

 

Lab experiments and Mini Project shall be done through Open source/ Licence free tools.

Registration

Selection will be based on ‘first come first serve basis’ among eligible registrants. Registration will be closed once sufficient number of candidates for a batch has registered.

Welcome mail will be sent by NIELIT Calicut to their registered email a day prior to start day of the course.

 

Registration Link :

https://www.calicut.nielit.in/OnlineCourseRegistration.aspx?c=LB-VSM3%2F2025%2F06%2F09

Support Desk

Course Coordinator:

Name : Mr. Sreejeesh SG, Senior Technical Officer

Contact Number : 9447769756

Mail ID : sree@calicut.nielit.in

 

Lab Support:

Mrs. Nanditha V, Adhoc Faculty

nanditha@calicut.nielit.in

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