Workshop on SoC Verification

SKU: NIELET Workshop | Start Date: March 25, 2024 Category:

Description

Design Verification in VLSI is a critical and time-intensive step in the product development process. Its primary goal is to ensure that the product or system design complies with specified standards and requirements. In fact, it typically accounts for about 80% of the total time allocated for the product development process. Many foundries place significant emphasis on testing and verification, which are crucial at every stage of VLSI design.

System Verilog is a hardware description and verification language that plays a crucial role in the field of electronic design automation (EDA) and integrated circuit (IC) design. It’s an extension of Verilog, which was originally developed for digital design and simulation. System Verilog adds powerful features specifically designed to facilitate verification, such as enhanced data types; object oriented programming capabilities, assertions, constraints, coverage and parallel or concurrent threads. This make system Verilog a vital tool in the development of complex digital systems

This course offers a comprehensive introduction to the primary enhancements that System Verilog brings to the Verilog hardware description language (HDL). It also illustrates the advantages of these new features and illustrates how design and verification processes can become more efficient and productive with the utilization of System Verilog constructs.

 

Session Date : 25th March, 2024

Duration : 65 Hours (Theory: 13 hours & Lab : 52 hours)

Lab Timings : 5 pm to 11 pm on weekdays 10 am to 11 pm on weekends

Profile of the Instructor(s)

Mr Nandakumar.R

Scientist ‘D’, NIELIT Calicut

 

Educational Qualifications:

M.E (ECE) , MBA

 

Total  EXPERIENCE: 15 Years

 

Position and Organization:

Scientist, NIELIT Calicut, Electronic System Engineering, VLSI/ASIC/IPCore Design, Training

Adhoc Faculty, NIT Calicut

 

AWARDS:

  1. IEEE Outstanding Young Professional Award (R10-Asia Pacific) 2015

 

R & D Labs Co-Established at NIELIT Calicut

  1. Advanced VLSI System Design Lab
  2. Chip to System Design Lab
  3. Swadeshi Microprocessor-based Remote Embedded System Design Lab
  4. Skilled Manpower Advance Research and Training (SMART) Facility

 

 

Mr Sreejeesh SG

Senior Technical Officer, NIELIT Calicut

 

Educational Qualifications:

M.Tech (By Research), B.Tech (ECE)

 

R&D EXPERIENCE: 15+Years 

 

Position and Organization:

Senior Technical Officer, NIELIT Calicut (VLSI/FPGA/ASIC/IPCore Design, Training) – 15 years.

 

R & D Labs Co-Established at NIELIT Calicut

  1. Advanced VLSI System Design Lab
  2. Funded R & D Lab for Medical Ultrasound research
  3. Chip to System Design Lab
  4. Swadeshi Microprocessor-based Remote Embedded System Design Lab
  5. Skilled Manpower Advance Research and Training (SMART) Facility

Topics Covered

  1. Introduction to Verification and System Verilog.
  2. Data Types in System Verilog
  3. Procedural and Flow Control statement in System Verilog
  4. System Verilog FORK and JOIN statements.
  5. Object oriented Programming Concepts in System Verilog.
  6. Randomization and Constraints in System Verilog.
  7. Assertions in System Verilog
  8. Verification of combinational and Sequential Circuits using System Verilog.
  9. Verification of IPs based on AHB Lite/ APB/AXI using system Verilog.

Intended Audience

Engineering students, recent graduates and young professionals with back ground in Digital Electronics.

Perquisites for the program

Verilog HDL Knowledge / Lab Workshop on  FPGA Architecture and Programming using Verilog HDL /Lab Workshop on ARM Based SoC Design/Lab Workshop on Advanced ARM SoC Design.

Certification

50 % for assignments and 50 % for exit test

Mode of Delivery

Theory sessions shall be delivered through ONLINE mode using recorded lectures by NPTEL.

Lab demo (recorded) and live sessions shall be delivered through ONLINE mode by NIELIT Calicut.

Lab experiments and Mini Project shall be done through the Remote SMART lab at NIELIT Calicut.

Registration

Selection will be based on ‘first come first serve basis’ among eligible registrants. Registration will be closed once sufficient number of candidates for a batch has registered.

Welcome mail will be sent by NIELIT Calicut to their registered email a day prior to start day of the course.

 

Registration Link :

https://pages.razorpay.com/pl_MkT353aG6CH7ZE/view

Support Desk

Workshop Coordinator: 

Name : R. Nandakumar

Phone : 9995427802

Mail ID : nanda@nielit.gov.in, nanda@calicut.nielit.in

 

 

For Queries/Support : 

Name : S.G Sreejeesh

Phone : 9447769756

Mail ID : sreejeesh@nielit.gov.in, sree@calicut.nielit.in

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